Cadence OrCAD PCB design suites combine industry-leading, production-proven, and highly scalable PCB design applications to deliver complete schematic entry, simulation, and place-and-route solutions. With these powerful, intuitive tools that integrate seamlessly across the entire PCB design flow, engineers can quickly move products from conception to final output.
To stay competitive in todayâs market, companies must move their designs from engineering to manufacturing within ever-shrinking design schedules. Available as standalone products or in comprehensive suites, cadence OrCAD personal productivity tools have a long history of addressing PCB design challenges, whether simple or complex. The powerful, tightly integrated PCB design technologies include OrCAD Capture for schematic design, various librarian tools, OrCAD PCB Editor for place and route, PSpice A/D for circuit simulation, OrCAD PCB SI for signal integrity analysis, and SPECCTRA for OrCAD for automatic routing. Easy to use and intuitive, these tools bring exceptional value and future-proof scalability to the Cadence Allegro system interconnect design platform to grow with future design demands. OrCAD PCB design suites provide integrated front-end design and simulation technology (Cadence OrCAD EE Designer) as well as an integrated back-end place-and-route design solution (Cadence OrCAD PCB Designer) to boost productivity and accelerate time to market.
DATE: 06-20-2012 HOTFIX VERSION: 024
CCRID PRODUCT PRODUCTLEVEL2 TITLE
982824 ALLEGRO_EDITOR OTHER Import placement fails with a zero length log file.
1006437 SIP_LAYOUT BGA_EDITOR SCM not loading the die if dies refdes and LFnames are changed
1011040 FSP PROCESS Feature to avoid connectivity between fixed voltage Output and variable voltage Input
1012985 ALLEGRO_EDITOR DATABASE Allegro crashes multiple times a day
1013644 ALLEGRO_EDITOR SHAPE Sliding trace with oops creates a duplicate shape islands
1014351 ALLEGRO_EDITOR OTHER Whenever we open a file (brd, dra) in PCB Editor with an OrCAD PCB Designer license,we get a warning SPMH0D-34
1014893 CONSTRAINT_MGR OTHER With CM open layout is extremely slow and Allegro crashes very frequently
1015210 ALLEGRO_EDITOR DRC_CONSTR Deleting Via from an array casues DRC errors
1016546 CONCEPT_HDL CONSTRAINT_MGR Wrong value of NET_PYSICAL _SPACING_TYPE in Attribute form
1016932 RF_PCB DISCRETE_LIBX_2A Incorrect Symbol Pin Numbers after import into ADS
1017332 APD VIA_STRUCTURE Refreshing Via Structures results in shorting to power plane.
1017931 ALLEGRO_EDITOR OTHER IPF import fails with error-IPF error : Illegal pen number
1018413 F2B PACKAGERXL Export Physical producing different results depending on how it is launched
1018435 APD OTHER Oblong pads in Sip are not displayed correctly in the Stream_out .sf file.
1018936 ALLEGRO_EDITOR OTHER unexpexted DRC eror
1018978 ALLEGRO_EDITOR DRC_CONSTR Update DRC changes DRC without any change in design
1019303 CONCEPT_HDL INFRA DEHDL custom outport displays error
1019913 ALLEGRO_EDITOR DATABASE BUG:Bottom pins are also shown in DXF export
1019955 ALLEGRO_EDITOR SKILL axlRegionCreate and axlRegionAdd do not work in a symbol file.
1020749 ALLEGRO_EDITOR DATABASE 16.2 Parts not updating when opened in a 16.5 database
1020780 APD COLOR APD crash on assigning color to net using Color192
1021033 CONCEPT_HDL CONSTRAINT_MGR Cleared ecsets in 16.3 reappears as mapping errors without ecset names after uprev to 16.5
About Cadence Design Systems, Inc.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
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